1. Field of the Invention
The invention relates to a method of designating an output xe2x80x9cdon""t carexe2x80x9d in logic circuit data, an apparatus for doing the same, a processor for carrying out an equivalency test or synthesizing logics, and a method of carrying out an equivalency test or synthesizing logics, and more particularly to such a method, an apparatus and a processor all suitable for effectively carrying out an equivalency test for logic circuit data and effectively producing logic circuit data used for logic synthesis. The invention relates further to a recording medium readable by a computer, storing a program therein for causing a computer to carry out the above-mentioned methods or act as the above-mentioned apparatus or processor.
2. Description of the Related Art
Various methods have been suggested for testing equivalency between two logic circuits. In one of such methods, two logic circuits are converted into logic functions, and those logic functions are judged as to whether they are equivalent to each other.
FIG. 1 is a block diagram of a conventional system for carrying out an equivalency test.
The illustrated system is accomplished by a computer operating in accordance with a program. Specifically, the illustrated system is comprised of a graphic display 1, a keyboard 2, a mouse 3, an external memory 4, and a tester 101. The tester 101 is comprised of an input unit 102 including a logic circuit data reader 105 and a data form converter 106, an equivalency tester 103, and an internal database 104.
The logic circuit data reader 105 reader reads both logic circuit data used as reference data in judgment of equivalency with other data and logic circuit data judged as to whether equivalent to the reference data, out of the external memory 4, and stores the thus read-out logic circuit data into the internal database 104. Hereinafter, logic circuit data used as reference data in judgment of equivalency with other data is referred to as xe2x80x9creference logic circuit dataxe2x80x9d, and logic circuit data which is to be judged as to whether it is equivalent to the reference logic circuit data by comparing to the reference logic circuit data is referred to as xe2x80x9ctested logic circuit dataxe2x80x9d. Both the reference and tested logic circuit data are described by HDL which is a language by which a hardware is described, logic formula, a table of truth value, data about gate level connection, and so on.
The reference and tested logic circuit data are read out of the internal database 104, and are converted by the data form converter 106 into data having a form conforming to an equivalency test carried out by the equivalency tester 103. The thus converted reference and tested logic circuit data are judged by the equivalency tester 13 as to whether they are logically equivalent to each other.
In a usual case wherein an equivalency test is carried out to gate-leveled
In a usual case wherein an equivalency test is carried out to gate-leveled logic circuit data logically synthesized from register/transfer-leveled original logic circuit data, the register/transfer-leveled original circuit data is used as the reference logic circuit data, and the gate-leveled logic circuit data is tested as to whether it is logically equivalent to the reference logic circuit data by comparing to the register/transfer-leveled original circuit data.
If the reference or tested logic circuit data includes an undefined output xe2x80x9cXxe2x80x9d among outputs derived therefrom, the equivalency tester 103 judges that the reference and tested logic circuit data are logically equivalent to each other, when the reference logic circuit data outputs an defined value xe2x80x9cXxe2x80x9d, even if the tested logic circuit data outputs an undefined value xe2x80x9cXxe2x80x9d, a logical value xe2x80x9c0xe2x80x9d or a logical value xe2x80x9c1xe2x80x9d.
On the other hand, when the tested logic circuit data outputs an undefined value xe2x80x9cXxe2x80x9d, the equivalency tester 103 judges that the reference and tested logic circuit data are logically equivalent to each other, only when the reference logic circuit data outputs an undefined value xe2x80x9cXxe2x80x9d, but judges that the reference and tested logic circuit data are not logically equivalent to each other, when the reference logic circuit data outputs a value other than an undefined value xe2x80x9cXxe2x80x9d, such as a logical value xe2x80x9c0xe2x80x9d.
That is, the reference and tested logic circuit data are judged logically equivalent to each other only when both the reference and tested logic circuit data output a logical value either xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d.
However, for instance, when the reference and tested logic circuit data are gate-leveled logic circuit data synthesized from register/transfer-leveled original logic circuit data including xe2x80x9cdon""t carexe2x80x9d logic, under different conditions, the reference and tested logic circuit data may not be equivalent to each other in an equivalency test.
Herein, xe2x80x9cdon""t carexe2x80x9d logic indicates an output which exerts no influence on results of logical operation carried out by subsequent circuits regardless of a value of an output node.
FIG. 2 illustrates an example of synthesizing logic, based on logic circuit data including xe2x80x9cdon""t carexe2x80x9d logic.
In FIG. 2, logic circuit data 112 of a logic circuit (A) produced by logic synthesis on the basis of original logic circuit data 111 under constraint conditions (A) is used as reference logic circuit data, and logic circuit data 113 of a logic circuit (B) produced by logic synthesis on the basis of original logic circuit data 111 under constraint conditions (B) is tested as to whether the logic circuit data 113 is logically equivalent to the logic circuit data 112.
In an equivalency test between the logic circuit data 112 and 113, since an undefined value xe2x80x9cXxe2x80x9d in the original logic circuit data 111 may be a logical value xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, the logic circuit data 112 has to be judged logically equivalent to the logic circuit data 113. However, since the logic circuit data 112 and 113 are apparently different from each other, the equivalency test system illustrated in FIG. 1 judges that the logic circuit data 112 and 113 are not equivalent to each other.
In order to avoid such apparent mismatch in logic, caused by xe2x80x9cdon""t carexe2x80x9d logic, it is necessary to identify a node having xe2x80x9cdon""t carexe2x80x9d logic, and take necessary steps to the thus identified node in order to avoid mismatch in logic.
FIG. 3 is a flow chart of a conventional method of preventing such mismatch in logic, caused by xe2x80x9cdon""t carexe2x80x9d logic, and FIGS. 4A and 4B illustrate examples of steps carried out for preventing such mismatch in logic.
Hereinbelow, it is assumed that both reference logic circuit data and tested logic circuit data are described in HDL, and HDL in which reference logic circuit data and tested logic circuit data are described are referred to as reference data HDL and tested data HDL, respectively. Hereinbelow are explained steps in the method in FIG. 3 with reference to FIGS. 1, 4A and 4B.
With reference to FIG. 3, the logic circuit data reader 105 reads the tested data HDL out of the external memory 4 in step 121. If there is a technology library necessary for mapping a logic circuit described in the tested data HDL, the logic circuit data reader 105 reads the technology library, too.
Then, the logic circuit data reader 105 reads the reference data HDL out of the external memory 4 in the same way as step 121, in step 122.
Then, the data form converter 106 converts the tested data HDL into tested circuit data 131 having a form conforming to an equivalency test carried out in the equivalency tester 103, in step 123.
Then, the data form converter 106 converts the reference data HDL into reference circuit data 133 having a form conforming to an equivalency test carried out in the equivalency tester 103, in step 124.
Then, an operator finds out a node in which xe2x80x9cdon""t carexe2x80x9d is established (hereinbelow, such a node is referred to as xe2x80x9cdon""t care nodexe2x80x9d), in step 125, and designates a logical value or removes the don""t care node out of an equivalency test such that the reference circuit data 133 and the tested circuit data 131 are coincident with each other in an equivalency test.
Then, the equivalency tester 103 carries out an equivalency test to judge whether the reference circuit data 133 and the tested circuit data 131 are logically equivalent to each other, in step 126. The results of the equivalency test are transmitted to the graphic display 1 and/or the external memory 4.
However, the above-mentioned method of avoiding mismatch in logic, illustrated in FIG. 3 is accompanied with the following problems.
The first problem is that it takes much time to detect a node of the reference data HDL associated with a node of the tested data HDL. A name of a node of the reference data HDL and a name of a node of the tested data HDL are automatically produced by logic synthesis, based on original logic circuit data HDL. Hence, the nodes are not always named such that an associated node can be readily detected, resulting in that an associated node has to be traced on the basis of an original logic circuit HDL.
The second problem is that designer""s knowledge and a great number of steps are required for carrying out an equivalency test to xe2x80x9cdon""t carexe2x80x9d logic. It is necessary to designate a logical value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d in some cases and to remove a don""t care node out of an equivalency test in other cases. That is, knowledge about an operation of the reference and tested logic circuits both produced by logic synthesis is required to do so. If a don""t care node is removed out of an equivalency test, it would be impossible to carry out an equivalency test to circuits located downstream of a don""t care node.
FIG. 4A illustrates an entirety of a tested logic circuit, and FIG. 4B illustrates an entirety of a reference logic circuit.
Since the tested circuit data 131 and the reference circuit data 133 transmit different outputs C from each other when inputs (A, B) is equal to (0, 1) or (1, 0), the outputs C associated with the inputs have to be dealt with as xe2x80x9cdon""t carexe2x80x9d. It would be possible to coincide an output CC transmitted from the tested circuit data 131 and an output CR transmitted from the reference circuit data 133 with each other and further coincide an output DC transmitted from an AND circuit 132 in a tested circuit and an output DR transmitted from an AND circuit 134 in a reference circuit with each other by changing a logical value of the output C associated with the input (A, B)=(0, 1) in the tested circuit data 131, into a logical value xe2x80x9c0xe2x80x9d and by changing a logical value of the output C associated with the input (A, B)=(1, 0) in the reference circuit data 133, into a logical value xe2x80x9c0xe2x80x9d.
However, an operator could not do so, unless the operator had deep knowledge about an operation of the reference and tested circuits.
Japanese Unexamined Patent Publication No. 11-3361 has suggested a method of carrying out an equivalency test without necessity of manually searching a node in logic circuit data including don""t care logic and changing a logical value.
FIG. 5 is a block diagram of a circuit for carrying out the above-mentioned method suggested in Japanese Unexamined Patent Publication No. 11-3361.
The circuit is comprised of a reference circuit 141, a tested circuit 142, a circuit 143 for judging whether logical values transmitted from the reference circuit 141 and the tested circuit 142 are coincident with each other, a xe2x80x9cdon""t carexe2x80x9d function 144, and an OR circuit 145.
In operation, outputs transmitted from the reference circuit 141 and the tested circuit 142 are input into the circuit 143, and an output transmitted from the circuit 143 and the xe2x80x9cdon""t carexe2x80x9d function 144 are input into the OR circuit 145.
When an output logical value transmitted from the tested circuit 142 and an output logical value transmitted from the reference circuit 141 are coincident with each other in response to a combination of an input logical value A xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d and an input logical value B xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, the circuit 143 outputs a logical value xe2x80x9c1xe2x80x9d. The OR circuit 145 transmits a logical value xe2x80x9c1xe2x80x9d as an output CHK. Hence, it is judged that the reference circuit 141 and the tested circuit 142 are equivalent to each other.
When an output logical value transmitted from the tested circuit 142 is different from an output logical value transmitted from the reference circuit 141, the circuit 143 outputs a logical value xe2x80x9c0xe2x80x9d. However, since the don""t care function 144 transmits a logical value xe2x80x9c1xe2x80x9d to the OR circuit 145, if the outputs transmitted from the circuits 141 and 142 are don""t care outputs, the OR circuit 145 transmits a logical value xe2x80x9c1xe2x80x9d as the output CHK. As a result, it is judged that the reference circuit 141 and the tested circuit 142 are equivalent to each other.
Only when an output logical value transmitted from the tested circuit 142 is different from an output logical value transmitted from the reference circuit 141 and the outputs transmitted from the circuits 141 and 142 are not registered in the don""t care function 144 as don""t care data, the OR circuit 145 transmits a logical value xe2x80x9c0xe2x80x9d as the output CHK, resulting in that the reference circuit 141 and the tested circuit 142 are judged not equivalent to each other.
Thus, the method makes it possible to carry out an equivalency test to logic circuit data including don""t care logic, without any steps manually performed by an operator.
However, the above-mentioned method suggested in Japanese Unexamined Patent Publication No. 11-3361 is accompanied with a problem that it is necessary that an equivalency test has to be carried out to a circuit in its entirety from an input terminal to an output terminal or a circuit in its entirety from a register to an adjacent register, and hence, it is impossible to divide a circuit into smaller-sized circuits for carrying out an equivalency test.
For instance, if the tested circuit including the tested circuit data 131 and the AND circuit 132, illustrated in FIG. 4A, and the reference circuit including the reference circuit data 133 and the AND circuit 134, illustrated in FIG. 4B, are to be judged whether equivalent to each other in accordance with the above-mentioned method by dividing the tested and reference circuits into unit circuits, the tested circuit data 131 and the reference circuit data 133 are first extracted, and then, the above-mentioned method are applied to the thus extracted data 131 and 133.
Thus, there are obtained results that the output CC transmitted from the tested circuit data 131 and the output CR transmitted from the reference circuit data 133 are equivalent to each other.
However, when it is judged as to whether an output transmitted from the AND circuit 132 and an output transmitted from the AND circuit 134 are equivalent to each other, since different input signal names are input into the AND circuits 132 and 134, the outputs transmitted from the AND circuits 132 and 134 are judged not equivalent to each other.
Accordingly, when an equivalency test is to be carried out in accordance with the above-mentioned method, an equivalency test has to be carried out to the tested circuit in its entirety including the tested circuit data 131 and the AND circuit 132 and the reference circuit in its entirety including the reference circuit data 133 and the AND circuit 134. If an equivalency test is to be carried out to divided circuits of the tested or reference circuit, an accuracy in results of an equivalency test is not always ensured.
As mentioned above, the method suggested in Japanese Unexamined Patent Publication No. 11-3361 is accompanied with a problem that an equivalency test has to be carried out per a large unit of a circuit, and hence, if circuits are judged not equivalent to each other in an equivalency test, it would be quite difficult to analyze the reason of no equivalency and identify a non-equivalent part in the tested circuits.
In accordance with the conventional method illustrated in FIGS. 1 to 4B, a node in one of the reference data HDL and the tested data HDL both synthesized on the basis of original circuit HDL could be readily associated with a node in the original circuit HDL. Hence, if xe2x80x9cdon""t carexe2x80x9d logic could be readily designated for a xe2x80x9cdon""t carexe2x80x9d node in the original circuit HDL, an equivalency test could be carried out without manually changing logic circuit data by removing a xe2x80x9cdon""t carexe2x80x9d output out of an equivalency test with respect to a xe2x80x9cdon""t carexe2x80x9d node, and transferring an original output to a next stage logic circuit as an input logical value. In addition, an equivalency test could be carried out to divided circuits.
Furthermore, if an operator could readily designate any node as a xe2x80x9cdon""t carexe2x80x9d node to thereby designate xe2x80x9cdon""t carexe2x80x9d logic, it would be possible to alter design of a xe2x80x9cdon""t carexe2x80x9d node and xe2x80x9cdon""t carexe2x80x9d logic, resulting in that secondary logic circuit data could be effectively produced by partially removing original logic circuit data.
Japanese Unexamined Patent Publication No. 6-68194 has suggested a method of identifying undefined data out of functional description, comprising the steps of analyzing input functional description and extracting data flow and control data, retrieving substitution relation and reference conditions on the basis of the data flow and the control data, and extracting undefined data on the basis of the reference conditions.
Japanese Unexamined Patent Publication No. 9-128431 has suggested an equivalency testing system for carrying out an equivalency test between two logic circuits each including a sequential circuit, including means for rewriting circuit description of two circuits to be tested, in order to obviously show initial conditions of the circuits. The circuits are judged whether equivalent to each other by comparing circuit description in which the initial conditions are explicitly described.
Japanese Unexamined Patent Publication No. 9-319782 has suggested a method of testing a sequential logic apparatus. The method makes it possible to carry out an equivalency test per a command, and to convert Boolean equation into arithmetic expression.
Japanese Unexamined Patent Publication No. 10-269256 has suggested an equivalency tester for carrying out an equivalency test among a plurality of logic circuits, including first means for producing stationary finite-state machines (FMS) associated with the logic circuits, based on circuit description in which the logic circuits are described, and data about signals input into the logic circuits, an equivalency tester which carries out a logic equivalency test to the stationary finite-state machines, and an output unit which outputs results of the logic equivalency test having been carried out by the equivalency tester.
In view of the above-mentioned problems in the prior art, it is an object of the present invention to provide a method of designating a xe2x80x9cdon""t carexe2x80x9d node and xe2x80x9cdon""t carexe2x80x9d logic, which method makes it possible to more readily designate a xe2x80x9cdon""t carexe2x80x9d node and xe2x80x9cdon""t carexe2x80x9d logic than the conventional methods.
It is also an object of the present invention to provide a method and an apparatus for carrying out an equivalency test.
It is further an object of the present invention to provide a method and an apparatus for synthesizing logic.
In one aspect of the present invention, there is provided a method of designating an output xe2x80x9cdon""t carexe2x80x9d, including the steps of (a) reading first data about a logic circuit in which outputs associated a plurality of inputs are described, (b) reading xe2x80x9cdon""t carexe2x80x9d indicating data which outputs a predetermined logic value in response only to a specific input among the plurality of inputs, (c) coupling the plurality of inputs to associated inputs in the xe2x80x9cdon""t carexe2x80x9d indicating data, and (d) detecting an output in the first data which output is associated with the specific input.
There is further provided a method of designating an output xe2x80x9cdon""t carexe2x80x9d, including the steps of (a) reading first data about a logic circuit in which outputs associated a plurality of inputs are described, (b) reading xe2x80x9cdon""t carexe2x80x9d indicating data which outputs a predetermined logic value in response only to a specific input among the plurality of inputs, (c) converting the first data into second data having a form conforming to an application, (d) converting the xe2x80x9cdon""t carexe2x80x9d indicating data into third data having the form, (e) coupling the plurality of inputs in the second data to associated inputs in the third data, and (f) detecting an output in the second data which output is associated with an input in response to which the predetermined logic value is output from the xe2x80x9cdon""t carexe2x80x9d indicating data.
In another aspect of the present invention, there is provided an apparatus for designating an output xe2x80x9cdon""t carexe2x80x9d, including (a) a data reader which externally reads (b1) first logic circuit data which is to be judged as to whether equivalent to reference data, (b2) second logic circuit data used as reference data in judgment of equivalency with other data, and (b3) xe2x80x9cdon""t carexe2x80x9d indicating data which receives the same inputs as inputs received in the second data and which outputs a predetermined logic value in response only to an input associated with a xe2x80x9cdon""t carexe2x80x9d output, (b) a data form converter which converts the first logic circuit data, the second logic circuit data and the xe2x80x9cdon""t carexe2x80x9d indicating data into third, fourth and fifth data, respectively, each having a form conforming to an equivalency test, (c) a data coupler which couples an input in the fourth data to an associated input in the fifth data, and (d) an output detector which detects an output in the fourth data which output is associated with an input in response to which the fifth data outputs the predetermined logic value.
In still another aspect of the present invention, there is provided a processor including (a) an internal database storing logic circuit data therein, (b) a data reader which externally reads (b1) first logic circuit data which is to be judged as to whether equivalent to reference data, (b2) second logic circuit data used as reference data in judgment of equivalency with other data, and (b3) xe2x80x9cdon""t carexe2x80x9d indicating data which receives the same inputs as inputs received in the second data and which outputs a predetermined logic value in response only to an input associated with a xe2x80x9cdon""t carexe2x80x9d output, (c) a data form converter which converts the first logic circuit data, the second logic circuit data and the xe2x80x9cdon""t carexe2x80x9d indicating data into third, fourth and fifth data, respectively, each having a form conforming to an equivalency test, (d) a data coupler which couples an input in the fourth data to an associated input in the fifth data, (e) an output detector which detects an output in the fourth data which output is associated with an input in response to which the fifth data outputs the predetermined logic value, and (f) an equivalency tester which deems an output detected by the output detector, as an output having an undefined value, among outputs derived from the fourth data, and which judges whether an output derived from the third data is coincident with an output derived from the second data by comparing them to each other, with respect to outputs not detected by the output detector.
There is still further provided a method of processing logic circuit data, including the steps of (a) externally reading first logic circuit data which is to be judged as to whether equivalent to reference data, and storing the thus read first logic circuit data into an internal database, (b) externally reading second logic data used as reference data in judgment of equivalency with other data, and storing the thus read second logic circuit data into the internal database, (c) externally reading xe2x80x9cdon""t carexe2x80x9d indicating data which receives the same inputs as inputs received in the second logic circuit data and which outputs a predetermined logic value in response only to an input associated with a xe2x80x9cdon""t carexe2x80x9d output, and storing the thus read xe2x80x9cdon""t carexe2x80x9d indicating data into the internal database, (d) converting the first logic circuit data into third data having a form conforming to an equivalency test, (e) converting the second logic circuit data into fourth data having a form conforming to an equivalency test, (f) converting the xe2x80x9cdon""t carexe2x80x9d indicating data into fifth data having a form conforming to an equivalency test, (g) coupling an input in the fourth data to an associated input in the fifth data, and storing the thus coupled data into the internal database, (h) detecting an output in the fourth data which output is associated with an input in response to which the fifth data outputs the predetermined logic value, and (i) deeming an output detected by the step (h), as an output having an undefined value, among outputs derived from the fourth data, and judging whether an output derived from the third data is coincident with an output derived from the second data by comparing them to each other, with respect to outputs not detected by the step (h).
There is further provided a processor including (a) an internal database storing logic circuit data therein, (b) a data reader which externally reads (b1) original logic circuit data, and (b2) xe2x80x9cdon""t carexe2x80x9d indicating data which outputs a predetermined logic value in response only to a specific input among a plurality of outputs derived from the original logic circuit data, (c) a data form converter which converts the original logic circuit data and the xe2x80x9cdon""t carexe2x80x9d indicating data into first and second data, respectively, each having a form conforming to synthesis of logic, (d) a data coupler which couples an input in the first data to an associated input in the second data, (e) an output detector which detects an output derived from the first data which output is associated with an input in response to which the second data outputs the predetermined logic value, and converts the thus detected output into an undefined output as third data, and (f) a logic synthesizer which reads the third data thereinto for logic synthesis to thereby produce resultant synthesized logic circuit data.
There is yet further provided a method of processing logic circuit data, including the steps of (a) externally reading original logic data, and storing the thus read original logic data into an internal database, (b) externally reading xe2x80x9cdon""t carexe2x80x9d indicating data which outputs a predetermined logic value in response only to a specific input among a plurality of outputs derived from the original logic circuit data, and storing the thus read xe2x80x9cdon""t carexe2x80x9d indicating data into the internal database, (c) converting the original logic circuit data into first data having a form conforming to synthesis of logic, (d) converting the xe2x80x9cdon""t carexe2x80x9d indicating data into second data having a form conforming to synthesis of logic, (e) coupling an input in the first data to an associated input in the second data, (f) detecting an output derived from the first data which output is associated with an input in response to which the second data outputs the predetermined logic value, and converting the thus detected output into an undefined output as third data, and (g) synthesizing logic in accordance with the third data to thereby produce resultant synthesized logic circuit data.
In yet another aspect of the present invention, there is provided a recording medium readable by a computer, storing a program therein for causing a computer to carry out the above-mentioned method of designating an output xe2x80x9cdon""t carexe2x80x9d.
There is further provided a recording medium readable by a computer, storing a program therein for causing a computer to carry out the above-mentioned method of processing logic circuit data.
There is still further provided a recording medium readable by a computer, storing a program therein for causing a computer to act as the above-mentioned apparatus for designating an output xe2x80x9cdon""t carexe2x80x9d.
There is yet further provided a recording medium readable by a computer, storing a program therein for causing a computer to act as the above-mentioned processor.
The advantages obtained by the aforementioned present invention will be described hereinbelow.
In accordance with the above-mentioned method of designating xe2x80x9cdon""t carexe2x80x9d, it is possible to designate an output of logic circuit data which output is associated with an input in response to which xe2x80x9cdon""t carexe2x80x9d output data outputs a predetermined logical value, as an output status of an output xe2x80x9cdon""t carexe2x80x9d, by determining the predetermined logical value as an output value in desired output status. As a result, it would be possible to more readily designate xe2x80x9cdon""t carexe2x80x9d logic than the conventional methods.
In the method and apparatus for carrying out an equivalency test in accordance with the present invention, a xe2x80x9cdon""t carexe2x80x9d node and xe2x80x9cdon""t carexe2x80x9d logic may be designated to one of two logic circuit data to be tested, resulting in significant reduction in steps to be carried out relative to the conventional methods.
In addition, in accordance with the present invention, an equivalency test can be carried out to a circuit comprised of a plurality of circuits combined to one another, resulting in that it would be possible to more readily analyze the reason of non-equivalency and identify a non-equivalent part in tested circuits than the conventional methods, even if an equivalency test shows that tested circuits are not equivalent to each other.
The apparatus and method of synthesizing logic in accordance with the present invention makes it possible to produce a plurality of functional circuits having the same logic, from single original logic circuit data, resulting in enhancement in design efficiency and reduction in design errors.
The above and other objects and advantageous features of the present invention will be made apparent from the following description made with reference to the accompanying drawings, in which like reference characters designate the same or similar parts throughout the drawings.